Transistors consume power in two distinct ways: (1) during an OFF state (i.e., standby), when a leakage current flows through the transistor, even though it is not needed, and (2) during an ON/OFF switching operation, when surrounding circuits are charged and discharged due to a voltage change on the transistor that changes the transistor state between OFF and ON. To reduce power consumption, it is desirable to reduce both the leakage current present during the OFF state and the voltage swing used for the ON/OFF switching operation as much as possible. The ON/OFF voltage swing may be characterized by the subthreshold slope (“SS”), also sometimes referred to as the subthreshold swing. Conventional metal-oxide-silicon field-effect transistors (“MOSFETs”) are fundamentally limited to a lower bound SS of 60 mV/decade (at room temperature) that cannot be reduced.
Tunnel field-effect transistors (“TFETs”) or tunnel transistors have been designed to reduce the SS beyond this limit and, thereby, to allow further reductions in the ON/OFF voltage swing. In tunnel transistors, the cold injection of valence electrons located in a source contact into the conduction band of a drain contact (or vice versa) does not impose any theoretical lower limit to the SS. Most tunnel transistor designs, however, are based on lateral tunneling and suffer from relatively low ON currents, due to a small available tunneling area. More recently, tunnel transistors using a vertical band-to-band tunneling (“BTBT”) approach, similar to the gate induced drain leakage (“GIDL”) mechanism present in conventional MOSFETs, have been proposed. The vertical BTBT approach has the advantage of providing a large tunneling area, proportional to the gate length of the transistor, that should provide large ON currents. Thus, the vertical BTBT approach offers potential power savings as compared to conventional designs.
Nevertheless, proposed tunnel transistor designs face shortcomings Accordingly, it is desirable to provide methods for fabricating improved integrated circuits having tunnel transistors. Further, it is desirable to provide improved methods for fabricating integrated circuits having tunnel transistors. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.